Search - RS vhdl

[Applications] RS encoder(Verilog)

Description: RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
Platform: | Size: 5120 | Author: 王锋 | Hits:

[VHDL-FPGA-Verilog] gongcehngsheji_477-2

Description: 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Platform: | Size: 6144 | Author: 李超 | Hits:

[VHDL-FPGA-Verilog] RS_decoder

Description: rs编码vvhdl 希望能通过我不晓得具体对大家有用否希望懂rs编码的多多交流 -rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange
Platform: | Size: 15360 | Author: | Hits:

[VHDL-FPGA-Verilog] RS(32to28)encoderanddecoder

Description: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Platform: | Size: 76800 | Author: 王文 | Hits:

[Communication] URAT

Description: 最常见的rs232通信的vhdl实现，经过实际使用验证-The most common communication RS232 VHDL realize, through actual use of authentication
Platform: | Size: 32768 | Author: 江泽民 | Hits:

[Post-TeleCom sofeware systems] rs-code

Description: 基于PLD的RS码编译码器设计，用VHDL语言编写，编译通过，测试结果正确。-PLD-based encoding and decoding of RS code design, using VHDL language, the compiler is passed, the test results correctly.
Platform: | Size: 15360 | Author: li.j | Hits:

[VHDL-FPGA-Verilog] rs-5-3

Description: 学习使用FPGA做一些简单的编码器,RS(5,3)编码就是5个字符中有5-3=2两个校正字-Learning to use the FPGA to do a few simple encoders, RS (5,3) code is five characters in 5-3 = 2 has two correction words
Platform: | Size: 992256 | Author: rubyshirial | Hits:

[VHDL-FPGA-Verilog] RS232

Description: quatus II 环境下vhdl实现RS232功能-quatus II environment realize RS232 VHDL functional
Platform: | Size: 437248 | Author: 王艳华 | Hits:

[source in ebook] RSencode

Description: 包含RS（10，8）的verilog源程序，加法器的verilog源程序，卷积码的verilog源程序-Contains RS (10,8) of the Verilog source code, the Verilog source code adder, convolution of the Verilog source code
Platform: | Size: 1024 | Author: bai | Hits:

[VHDL-FPGA-Verilog] RS(204_188)decoder

Description: <Verilog HDL 语言编程》 RS(204,188)译码器的设计-<Verilog HDL language programming RS (204,188) Decoder
Platform: | Size: 11264 | Author: 李映波 | Hits:

[VHDL-FPGA-Verilog] rs-codec-8-16

Description: RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Platform: | Size: 27648 | Author: 饶进平 | Hits:

[VHDL-FPGA-Verilog] RS

Description: reed selemon encoder vhdl code
Platform: | Size: 77824 | Author: mohamed saad | Hits:

[Other] RS(204.188)design

Description: RS(204,188)译码器说明原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_power.mif（ROM初始化文件）。仿真波形： rs_decoder.vwf。-RS (204,188) decoder that the original document: rs_decoder.v (top-level document), SyndromeCalc.v (calculated Syndrome), BM_KES.v (BM key equation solving), Forney.v (Forney algorithm for error-like value), CheinSearch.v (search the wrong location), ff_mul.v (finite field multiplication). ROM and the initialization file: rom_inv.v (inverse operation), rom_power.v (for power calculations) rom_inv.mif (ROM initialization file), rom_power.mif (ROM initialization files). Simulation waveforms: rs_decoder.vwf.
Platform: | Size: 14336 | Author: 川天古木 | Hits:

[VHDL-FPGA-Verilog] RS-code

Description: 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
Platform: | Size: 983040 | Author: kiekie | Hits:

[VHDL-FPGA-Verilog] RS-5-3-CODE

Description: RS(5,3）编码器原程序程序已经调试过且比较简短-RS(5,3） coder ,this code is very short
Platform: | Size: 465920 | Author: ai锋聆 | Hits:

[VHDL-FPGA-Verilog] RS

Description: RS编码器的VHDL源程序,程序有点大，不过能用。-RS encoder VHDL source code, program a little big, but can be used.
Platform: | Size: 897024 | Author: lcz | Hits:

[VHDL-FPGA-Verilog] RS

Description: 基于FPGA的RS编码，包括RS码的编码原理，RS电路的设计与实现-FPGA-based RS code, including the RS, the coding principle, RS Circuit Design and Implementation
Platform: | Size: 1132544 | Author: 陈凯 | Hits:

[VHDL-FPGA-Verilog] RS

Description: RS译码器的设计，使用RS码设计的译码器-RS decoder design, the use of RS code decoder design
Platform: | Size: 12288 | Author: 许皓天 | Hits:

[VHDL-FPGA-Verilog] rs-enc-255-239

Description: rs encoder21-rs encoder2111111111222222222222222222222222222222222
Platform: | Size: 2048 | Author: Root | Hits:

[ELanguage] rs(31-19)

Description: 本源代码是RS（31,19）编码器的顶端实现程序和测试程序，此程序可以验证编码器工作与否。此代码，已在ModelSim验证通过。并附上测试时所产生的结果图像。-Source code is RS (31,19) encoder to achieve the top programs and testing procedures, this program can verify the encoder to work or not. This code has been verified in ModelSim. Together with the result when the test images.
Platform: | Size: 376832 | Author: jianghong | Hits:

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[Applications] RS encoder(Verilog)

[VHDL-FPGA-Verilog] gongcehngsheji_477-2

[VHDL-FPGA-Verilog] RS_decoder

[VHDL-FPGA-Verilog] RS(32to28)encoderanddecoder

[Communication] URAT

[Post-TeleCom sofeware systems] rs-code

[VHDL-FPGA-Verilog] rs-5-3

[VHDL-FPGA-Verilog] RS232

[source in ebook] RSencode

[VHDL-FPGA-Verilog] RS(204_188)decoder

[VHDL-FPGA-Verilog] rs-codec-8-16

[VHDL-FPGA-Verilog] RS

[Other] RS(204.188)design

[VHDL-FPGA-Verilog] RS-code

[VHDL-FPGA-Verilog] RS-5-3-CODE

[VHDL-FPGA-Verilog] RS

[VHDL-FPGA-Verilog] RS

[VHDL-FPGA-Verilog] RS

[VHDL-FPGA-Verilog] rs-enc-255-239

[ELanguage] rs(31-19)

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